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Microcontroladores (MCU) y procesadores
Procesadores digitales de señales (DSP)

DM383

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Procesador de medios digitales DaVinci

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DM383

COMPRA POR ÚLTIMA VEZ
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Detalles del producto

DSP type 0 Operating system Linux, PrOS Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 0 Operating system Linux, PrOS Rating Catalog Operating temperature range (°C) 0 to 0
FCCSP (AAR) 609 256 mm² 16 x 16
  • High-Performance DaVinci Digital Media Processors
    • Up to 1000-MHz ARM® Cortex™-A8 RISC Processor
    • Up to 2000 ARM Cortex-A8 MIPS
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache with ECC
    • 64KB of RAM, 48KB of Boot ROM
  • 256KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
      • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect (FD) Engine
    • Hardware Face Detection for up to 35 Faces Per Frame
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS, HDVICP2, and ISS
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Inputs
      • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
      • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
    • Component HD Analog Output
    • Composite Analog Output
    • Digital HDMI 1.3 Transmitter with Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
    • Three Graphics Layers and Compositors
  • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
    • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
    • Up to Two x 16 Devices, 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Total Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels
    • 8 QDMA Channels
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts
    • Supports End Points 0-15
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Three Configurable UART/IrDA/CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
    • Each with Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
    • Supporting up to 1-, 4-, or 8-Bit Modes
  • Dual Controller Area Network (DCAN) Module
    • CAN Version 2 Part A, B
  • Four Inter-Integrated Circuit (I2C Bus™) Ports
  • Two Multichannel Audio Serial Ports (McASP)
    • Six Serializer Transmit and Receive Ports
    • Two Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
    • Direct Interface to 1 Hard Disk Drive
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 125 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex™ Technology (Level 2b)
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Multiple Operating Points per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
  • 45-nm CMOS Technology
  • 1.8- and 3.3-V Dual Voltage Buffers for General I/O

All trademarks are the property of their respective owners.

  • High-Performance DaVinci Digital Media Processors
    • Up to 1000-MHz ARM® Cortex™-A8 RISC Processor
    • Up to 2000 ARM Cortex-A8 MIPS
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache with ECC
    • 64KB of RAM, 48KB of Boot ROM
  • 256KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
      • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect (FD) Engine
    • Hardware Face Detection for up to 35 Faces Per Frame
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS, HDVICP2, and ISS
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Inputs
      • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
      • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
    • Component HD Analog Output
    • Composite Analog Output
    • Digital HDMI 1.3 Transmitter with Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
    • Three Graphics Layers and Compositors
  • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
    • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
    • Up to Two x 16 Devices, 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Total Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels
    • 8 QDMA Channels
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts
    • Supports End Points 0-15
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Three Configurable UART/IrDA/CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
    • Each with Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
    • Supporting up to 1-, 4-, or 8-Bit Modes
  • Dual Controller Area Network (DCAN) Module
    • CAN Version 2 Part A, B
  • Four Inter-Integrated Circuit (I2C Bus™) Ports
  • Two Multichannel Audio Serial Ports (McASP)
    • Six Serializer Transmit and Receive Ports
    • Two Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
    • Direct Interface to 1 Hard Disk Drive
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 125 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex™ Technology (Level 2b)
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Multiple Operating Points per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
  • 45-nm CMOS Technology
  • 1.8- and 3.3-V Dual Voltage Buffers for General I/O

All trademarks are the property of their respective owners.

DM383 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of Car Black Box Digital Video Recorders, Portable Digital Video Recorders, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications.

The device enables original-design manufacturers (ODMs) and after-market manufacturers to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; two USB ports with integrated 2.0 PHY; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.

DM383 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of Car Black Box Digital Video Recorders, Portable Digital Video Recorders, and similar devices in SD and HD resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications.

The device enables original-design manufacturers (ODMs) and after-market manufacturers to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; two USB ports with integrated 2.0 PHY; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; two Controller Area Network (DCAN) modules; Serial ATA (SATA) 3.0 Gbps controller with integrated PHY; a Spin Lock; and Mailbox.

Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
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Documentación técnica

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Tipo Título Fecha
* Data sheet DM383 DaVinci Digital Media Processor datasheet (Rev. B) 18 dic 2013
* Errata DM383 DaVinci Digital Media Processor SE (Silicon Rev. 1.1, 1.0) 23 oct 2013
* User guide DM38x DaVinci™ Digital Media Processor Technical Reference Manual (Rev. B) 29 jun 2016
User guide DM38x DaVinci™ High-Definition Video Processing Subsystem (HDVPSS) (Rev. A) 30 jun 2016
User guide DM38x and TMS320DM8127 DaVinci™ Face Detect User's Guide (Rev. A) 30 jun 2016
User guide DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) User's Guide (Rev. A) 30 jun 2016

Diseño y desarrollo

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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