Inicio Lógica y traducción de voltaje Compuertas lógicas Compuertas AND
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Lógica y traducción de voltaje
Compuertas lógicas
Compuertas AND

SN74LVC1G08-Q1

ACTIVO

Compuerta AND automotriz de 1 canal y 2 entradas de 1.65 V a 5.5 V y 32 mA de potencia de accionamie

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SN74LVC1G08-Q1

ACTIVO
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Detalles del producto

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1: –40°C to +125°C, TA
  • Supports 5-V VCC Operation
  • Over-voltage Tolerant Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1: –40°C to +125°C, TA
  • Supports 5-V VCC Operation
  • Over-voltage Tolerant Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08-Q1 device performs the Boolean function or in positive logic.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the small DRY package with a body size of 1.45 mm × 1.00 mm.

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08-Q1 device performs the Boolean function or in positive logic.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the small DRY package with a body size of 1.45 mm × 1.00 mm.
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SN74AUP1G08-Q1 ACTIVO Compuerta AND automotriz de 1 canal y 2 entradas de 0.8 V a 3.6 V y baja potencia (<1 uA) Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

Documentación técnica

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* Data sheet SN74LVC1G08-Q1 Single 2-input positive-AND gate datasheet (Rev. G) PDF | HTML 20 may 2019
Application brief Optimizing ADAS Domain Controllers Using Logic and Translation PDF | HTML 13 jul 2023
Product overview Generate an Enable Signal that can be Toggled PDF | HTML 14 jun 2023
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Functional safety information SN74LVC1G08-Q1 Functional Safety FIT Rate and Failure Mode Distribution 30 dic 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
More literature Automotive Logic Devices Brochure 27 ago 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Placa de evaluación

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Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Placa de evaluación

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Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

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Guía del usuario: PDF
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Modelo de simulación

SN74LVC1G08 Behavioral SPICE Model

SCEM642.ZIP (7 KB) - PSpice Model
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Diseños de referencia

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This reference design provides a broadly-applicable automotive power design for a variety of ADAS processors, focusing on front and rear camera applications. The design supports an input range of 4 V to 48 V to supply common processor power rails through discrete components.  This adds to the (...)
Design guide: PDF
Esquema: PDF
Paquete Pasadores Descargar
SOT-23 (DBV) 5 Ver opciones
SOT-SC70 (DCK) 5 Ver opciones
USON (DRY) 6 Ver opciones
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Pedidos y calidad

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