Inicio Microcontroladores (MCU) y procesadores Microprocesadores y DSP SoC del procesador de señal digital (DSP) de radar y audio
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Microcontroladores (MCU) y procesadores
Microprocesadores y DSP
SoC del procesador de señal digital (DSP) de radar y audio

TMS320C6412

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DSP de punto fijo C64x de hasta 720 MHz, con McBSP, McASP, I2cC y Ethernet

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TMS320C6412

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Detalles del producto

CPU 32-/64-bit Frequency (MHz) 500, 600, 720 PCIe 1 PCI Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Frequency (MHz) 500, 600, 720 PCIe 1 PCI Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
OMFCBGA (GDK) 548 529 mm² (23 mm × 23 mm) OMFCBGA (ZDK) 548 529 mm² (23 mm × 23 mm) OMFCBGA (ZNZ) 548 729 mm² (27 mm × 27 mm)
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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Documentación técnica

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Ver todo 63
Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos TMS320C6412 Fixed-Point Digital Signal Processor datasheet (Rev. J) 12/10/2010
* Errata TMS320C641x, TMS320DM64x, TMS320DRA342 ZTS, ZNZ, ZDK Packages Discontinued and Converted PDF | HTML 9/02/2026
* Errata TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J) 4/02/2010
Nota sobre la aplicación How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19/05/2021
Guía del usuario Emulation and Trace Headers Technical Reference Manual (Rev. I) 9/08/2012
Nota sobre la aplicación Introduction to TMS320C6000 DSP Optimization 6/10/2011
Guía del usuario TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30/07/2010
Guía del usuario TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2/07/2009
Nota sobre la aplicación TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 4/09/2007
Nota sobre la aplicación Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20/05/2007
Guía del usuario TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11/04/2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 4/04/2007
Guía del usuario TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 26/03/2007
Guía del usuario TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) 25/01/2007
Guía del usuario TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14/12/2006
Guía del usuario TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15/11/2006
Guía del usuario TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 28/02/2006
Guía del usuario TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 1/01/2006
Nota sobre la aplicación TMS320C6412 Hardware Designer's Resource Guide (Rev. A) 21/10/2005
Nota sobre la aplicación Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20/10/2005
Guía del usuario TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 1/03/2005
Nota sobre la aplicación TMS320C6412 Power Consumption Summary (Rev. E) 27/01/2005
Guía del usuario TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25/01/2005
Nota sobre la aplicación Use and Handling of Semiconductor Packages With ENIG Pad Finishes 31/08/2004
Guía del usuario TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 13/08/2004
Nota sobre la aplicación TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26/04/2004
Nota sobre la aplicación TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21/04/2004
Guía del usuario TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 26/03/2004
Guía del usuario TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 25/03/2004
Nota sobre la aplicación TMS320C6000 McBSP Initialization (Rev. C) 8/03/2004
Nota sobre la aplicación TMS320C64x EDMA Performance Data 5/03/2004
Nota sobre la aplicación TMS320C6000 EDMA IO Scheduling and Performance 5/03/2004
Nota sobre la aplicación TMS320C64x EDMA Architecture 3/03/2004
Nota sobre la aplicación TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance 31/10/2003
Nota sobre la aplicación TMS320C64x DSP Host Port Interface (HPI) Performance 24/10/2003
Guía del usuario TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31/07/2003
Guía del usuario TMS320C6000 DSP Cache User's Guide (Rev. A) 5/05/2003
Nota sobre la aplicación Using IBIS Models for Timing Analysis (Rev. A) 15/04/2003
Nota sobre la aplicación TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 4/06/2002
Nota sobre la aplicación TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17/04/2002
Nota sobre la aplicación TMS320C6000 Board Design for JTAG (Rev. C) 2/04/2002
Nota sobre la aplicación TMS320C6000 EMIF to External Flash Memory (Rev. A) 13/02/2002
Nota sobre la aplicación Cache Usage in High-Performance DSP Applications with the TMS320C64x 13/12/2001
Nota sobre la aplicación Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31/10/2001
Nota sobre la aplicación TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24/10/2001
Nota sobre la aplicación Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30/09/2001
Nota sobre la aplicación TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30/09/2001
Nota sobre la aplicación Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31/08/2001
Nota sobre la aplicación TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31/08/2001
Nota sobre la aplicación TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31/08/2001
Nota sobre la aplicación TMS320C6000 System Clock Circuit Example (Rev. A) 15/08/2001
Nota sobre la aplicación TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23/07/2001
Nota sobre la aplicación TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10/07/2001
Nota sobre la aplicación TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30/06/2001
Nota sobre la aplicación TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21/06/2001
Nota sobre la aplicación TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21/05/2001
Guía del usuario TMS320C64x Technical Overview (Rev. B) 30/01/2001
Nota sobre la aplicación Circular Buffering on TMS320C6000 (Rev. A) 12/09/2000
Nota sobre la aplicación TMS320C6000 McBSP as a TDM Highway (Rev. A) 11/09/2000
Nota sobre la aplicación TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2/02/2000
Nota sobre la aplicación General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31/01/2000
Nota sobre la aplicación TMS320C6000 C Compiler: C Implementation of Intrinsics 7/12/1999
Nota sobre la aplicación TMS320C6000 McBSP: I2S Interface 8/09/1999

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

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La biblioteca de compatibilidad de chips (CSL) proporciona una interfaz de programación de aplicaciones (API) utilizada para configurar y controlar los periféricos del DSP en chip para facilitar el uso, la compatibilidad entre varios dispositivos C6000 y la abstracción de hardware. Esto acortará el (...)
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TELECOMLIB — Bibliotecas de telecomunicaciones y medios: FAXLIB, VoLIB y AEC/AER para procesadores TMS320C64x+ y

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ADT-3P-DSPVOIPCODECS — Tecnologías digitales adaptables DSP VOIP, códecs de voz y audio

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C6412 GDK/GNZ IBIS Model

SPRM110.ZIP (109 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

C6412 GNZ BSDL Model

SPRM122.ZIP (9 KB) - Modelo BSDL
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
OMFCBGA (GDK) 548 Ultra Librarian
OMFCBGA (ZDK) 548 Ultra Librarian
OMFCBGA (ZNZ) 548 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

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