TPS3813

The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems.

During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 25ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.

For safety critical applications the TPS3813xxx family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813xxx within this window not to assert a RESET.

The product spectrum is designed for supply voltages of 2.5V, 3V, 3.3V, and 5V. The circuits are available in a 6-pin SOT-23 package.

The TPS3813xxx devices are characterized for operation over a temperature range of –40°C to 85°C.