The TPS382x family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains less than the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to make sure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage (VIT− + VHYS). When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x family also offers watchdog time out options of 200ms (TPS3820) and 1.6s (TPS3823, TPS3824, and TPS3828).
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |
El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.
Si tiene alguna pregunta sobre calidad, encapsulados o pedido de productos de TI, consulte el servicio de asistencia de TI.