ADC08D1500

アクティブ

8 ビット、デュアル 1.5GSPS またはシングル 3.0GSPS の A/D コンバータ (ADC)

製品詳細

Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 47 ENOB (Bits) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 47 ENOB (Bits) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² (22 mm × 22 mm)
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Error Rate 10-18 (typ)
  • ENOB @ 748 MHz Input 7.25 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.8 W (typ)
    • Power Down Mode 3.5 mW (typ)

All trademarks are the property of their respective owners.

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Error Rate 10-18 (typ)
  • ENOB @ 748 MHz Input 7.25 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.8 W (typ)
    • Power Down Mode 3.5 mW (typ)

All trademarks are the property of their respective owners.

The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 C.E.R. Output formatting is binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 C.E.R. Output formatting is binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter データシート (Rev. G) 2013/04/18
アプリケーション・ノート AN-1558 Clocking High-Speed A/D Converters (Rev. B) 2013/05/01
アプリケーション・ノート 時間インタリーブ方式ADCシステム向け高精度クロックの生成 英語版 2007/08/02
アプリケーション・ノート Application Note 1558 Clocking High-Speed A/D Converters (jp) 2007/03/17
ホワイト・ペーパー High-Performance Analog Front Ends 2006/01/01
アプリケーション・ノート 高速信号とクロック、およびデータ・キャプチャを理解する 英語版 2005/10/18
アプリケーション・ノート Send High-Speed ADC Data Remotely And Quietly Using LVDS 2003/03/27

設計と開発

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シミュレーション・モデル

ADC08D1500 IBIS Model

SNAM007.ZIP (9 KB) - IBIS モデル
サポート対象の製品とハードウェア
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
HLQFP (NNB) 128 Ultra Librarian

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