ADC16DV160

アクティブ

デュアルチャネル、16 ビット、160-MSPS、A/D コンバータ (ADC)

製品詳細

Sample rate (max) (Msps) 160 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 2.4 Power consumption (typ) (mW) 1340 Architecture Pipeline SNR (dB) 78 ENOB (Bits) 12.3 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 160 Resolution (Bits) 16 Number of input channels 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 2.4 Power consumption (typ) (mW) 1340 Architecture Pipeline SNR (dB) 78 ENOB (Bits) 12.3 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
VQFNP (NKE) 68 100 mm² (10 mm × 10 mm)
  • Low Power Consumption
  • On-Chip Precision Reference and Sample-and-Hold Circuit
  • On-Chip Automatic Calibration During Power-Up
  • Dual Data Rate LVDS Output Port
  • Dual Supplies: 1.8V and 3.0V Operation
  • Selectable Input Range: 2.4 and 2.0 VPP
  • Sampling Edge Flipping with Clock Divider by 2 Option
  • Internal Clock Divide by 1 or 2
  • On-Chip Low Jitter Duty-Cycle Stabilizer
  • Power-Down and Sleep Modes
  • Output Fixed Pattern Generation
  • Output Clock Position Adjustment
  • 3-Wire SPI
  • Offset Binary or 2's Complement Data Format
  • 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 16 Bits
  • Conversion Rate: 160 MSPS
  • SNR (@FIN = 30 MHz): 78 dBFS (typ)
  • SNR (@FIN = 197 MHz): 76 dBFS (typ)
  • SFDR (@FIN = 30 MHz): 95 dBFS (typ)
  • SFDR (@FIN = 197 MHz): 89 dBFS (typ)
  • Full Power Bandwidth: 1.4 GHz (typ)
  • Power Consumption:
    • Core per channel: 612 mW (typ)
    • LVDS Driver: 117 mW (typ)
    • Total: 1.3W (typ)
  • Operating Temperature Range (-40°C ~ 85°C)
  • Low Power Consumption
  • On-Chip Precision Reference and Sample-and-Hold Circuit
  • On-Chip Automatic Calibration During Power-Up
  • Dual Data Rate LVDS Output Port
  • Dual Supplies: 1.8V and 3.0V Operation
  • Selectable Input Range: 2.4 and 2.0 VPP
  • Sampling Edge Flipping with Clock Divider by 2 Option
  • Internal Clock Divide by 1 or 2
  • On-Chip Low Jitter Duty-Cycle Stabilizer
  • Power-Down and Sleep Modes
  • Output Fixed Pattern Generation
  • Output Clock Position Adjustment
  • 3-Wire SPI
  • Offset Binary or 2's Complement Data Format
  • 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 16 Bits
  • Conversion Rate: 160 MSPS
  • SNR (@FIN = 30 MHz): 78 dBFS (typ)
  • SNR (@FIN = 197 MHz): 76 dBFS (typ)
  • SFDR (@FIN = 30 MHz): 95 dBFS (typ)
  • SFDR (@FIN = 197 MHz): 89 dBFS (typ)
  • Full Power Bandwidth: 1.4 GHz (typ)
  • Power Consumption:
    • Core per channel: 612 mW (typ)
    • LVDS Driver: 117 mW (typ)
    • Total: 1.3W (typ)
  • Operating Temperature Range (-40°C ~ 85°C)

The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.

The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs データシート (Rev. H) 2013/02/19
アプリケーション・ノート Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015/05/22
アプリケーション・ノート Signal Chain Noise Figure Analysis 2014/10/29
アプリケーション・ノート Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013/07/19
アプリケーション・ノート AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013/04/26
アプリケーション・ノート Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 2013/04/26
アプリケーション・ノート Between the Amplifier and ADC: Managing Filter Loss in Communications Systems (Rev. B) 2013/04/26
ユーザー・ガイド High-IF Sub-sampling Receiver Subsystem User Guide 2012/01/27

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