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CDC2536

アクティブ

1/2x、1x、2x の各周波数オプション、125MHz、3.3V、PLL クロック・ドライバ

ご注文はこちら
データシート

CDC2536

アクティブ
データシート ご注文はこちら

製品詳細

Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 6 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 500 Features Spread spectrum clocking (SSC) Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Zero-delay Additive RMS jitter (typ) (fs) 200 Output frequency (max) (MHz) 125 Number of outputs 6 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 500 Features Spread spectrum clocking (SSC) Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
SSOP (DB) 28 79.56 mm² 10.2 x 7.8
  • Low Output Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • Distributes One Clock Input to Six Outputs
  • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
  • No External RC Network Required
  • On-Chip Series Damping Resistors
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • Application for Synchronous DRAM, High-Speed Microprocessor
  • TTL-Compatible Inputs and Outputs
  • Outputs Drive 50- Parallel-Terminated Transmission Lines
  • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • Packaged in Plastic 28-Pin Shrink Small-Outline Package

EPIC-IIB is a trademark of Texas Instruments.
  • Low Output Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • Distributes One Clock Input to Six Outputs
  • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
  • No External RC Network Required
  • On-Chip Series Damping Resistors
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • Application for Synchronous DRAM, High-Speed Microprocessor
  • TTL-Compatible Inputs and Outputs
  • Outputs Drive 50- Parallel-Terminated Transmission Lines
  • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • Packaged in Plastic 28-Pin Shrink Small-Outline Package

EPIC-IIB is a trademark of Texas Instruments.

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external termination components.

The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.

Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of all outputs via OE\.

The CDC2536 is characterized for operation from 0°C to 70°C.

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external termination components.

The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.

Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of all outputs via OE\.

The CDC2536 is characterized for operation from 0°C to 70°C.
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート CDC2536: 3.3-V PLL Clock Driver With 3-State Outputs データシート (Rev. E) 2004年 7月 9日
アプリケーション・ノート Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers 1996年 4月 1日

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シミュレーション・モデル

CDC2536 IBIS Model

SCAC052.ZIP (30 KB) - IBIS Model
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