DAC2902

アクティブ

デュアルチャネル、12 ビット、125MSPS、D/A コンバータ (DAC)

製品詳細

Resolution (Bits) 12 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 125 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 310 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
Resolution (Bits) 12 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 125 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 310 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
TQFP (PFB) 48 81 mm² (9 mm × 9 mm)
  • 125MSPS UPDATE RATE
  • SINGLE SUPPLY: +3.3V or +5V
  • HIGH SFDR: 70dB at fOUT = 20MHz
  • LOW GLITCH: 2pVs
  • LOW POWER: 310mW
  • INTERNAL REFERENCE
  • POWER-DOWN MODE: 23mW
  • APPLICATIONS
    • COMMUNICATIONS:
          Base Stations, WLL, WLAN
          Baseband I/Q Modulation
    • MEDICAL/TEST INSTRUMENTATION
    • ARBITRARY WAVEFORM GENERATORS (ARB)
    • DIRECT DIGITAL SYNTHESIS (DDS)

  • 125MSPS UPDATE RATE
  • SINGLE SUPPLY: +3.3V or +5V
  • HIGH SFDR: 70dB at fOUT = 20MHz
  • LOW GLITCH: 2pVs
  • LOW POWER: 310mW
  • INTERNAL REFERENCE
  • POWER-DOWN MODE: 23mW
  • APPLICATIONS
    • COMMUNICATIONS:
          Base Stations, WLL, WLAN
          Baseband I/Q Modulation
    • MEDICAL/TEST INSTRUMENTATION
    • ARBITRARY WAVEFORM GENERATORS (ARB)
    • DIRECT DIGITAL SYNTHESIS (DDS)

The DAC2902 is a monolithic, 12-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW.

Operating with high update rates of up to 125MSPS, the DAC2902 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for "Direct IF" applications. The DAC2902 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight gain and offset matching.

Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2902 combines high dynamic performance with a high throughput rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:

  • Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.
  • Pin compatible to the AD9765 dual DAC.
  • Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.
  • The DAC2902 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.
  • All digital inputs are +3.3V and +5V logic compatible. The DAC2902 has an internal reference circuit, and allows use of an external reference.
  • The DAC2902 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C.

The DAC2902 is a monolithic, 12-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only 310mW.

Operating with high update rates of up to 125MSPS, the DAC2902 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for "Direct IF" applications. The DAC2902 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight gain and offset matching.

Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2902 combines high dynamic performance with a high throughput rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:

  • Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.
  • Pin compatible to the AD9765 dual DAC.
  • Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.
  • The DAC2902 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.
  • All digital inputs are +3.3V and +5V logic compatible. The DAC2902 has an internal reference circuit, and allows use of an external reference.
  • The DAC2902 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C.

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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート Dual, 12-Bit, 125MSPS Digital-to-Analog Converter データシート (Rev. C) 2008/09/19
アナログ デザイン ジャーナル Q4 2009 Issue Analog Applications Journal 2018/09/24
アプリケーション・ノート Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 2015/05/08
アナログ デザイン ジャーナル Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs 2009/10/04

設計と開発

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計算ツール

MATCHGAIN-CALC — Wideband Comp Current Output DAC to SE Interface: Impr Matching for Gain ; Compliance Volt Swing

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High-speed digital-to-analog converters (DACs) most often use a (...)

サポート対象の製品とハードウェア
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
TQFP (PFB) 48 Ultra Librarian

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