LM5115
- Self-Synchronization to Main Channel Output
- Standalone DC/DC Synchronous Buck Mode
- Leading Edge Pulse Width Modulation
- Voltage-Mode Control with Current Injection and Input Line Feed-Forward
- Operates from AC or DC Input up to 75V
- Wide 4.5V to 30V Bias Supply Range
- Wide 0.75V to 13.5V Output Range.
- Top and Bottom Gate Drivers Sink 2.5A Peak
- Adaptive Gate Driver Dead-Time Control
- Wide Bandwidth Error Amplifier (4MHz)
- Programmable Soft-Start
- Thermal Shutdown Protection
- TSSOP-16 or Thermally Enhanced WSON-16 Packages
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The LM5115 is a versatile switching regulator controller. It has two main application configurations. The first is utilizing the Secondary Side Post Regulation (SSPR) technique to implement multiple output power converters. In the second configuration, it can be used as a standalone synchronous buck controller (Please see for more details). The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of the main output. The LM5115 drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide common mode input range. Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead time control of the gate signals and thermal shutdown.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | LM5115 Secondary Side Post Regulator / Synchronous Buck Controller データシート (Rev. E) | 2013/03/21 | |||
| ホワイト・ペーパー | Valuing wide VIN, low EMI synchronous buck circuits for cost-driven, demanding a (Rev. A) | 2019/04/10 | ||||
| アナログ デザイン ジャーナル | Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics | 2016/07/21 |
設計と開発
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| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| WSON (NHQ) | 16 | Ultra Librarian |
購入と品質
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