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SN74ABT16863

アクティブ

3 ステート出力付き 18 ビット バス トランシーバ

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データシート

SN74ABT16863

アクティブ
ご注文はこちら

製品詳細

Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type TTL Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² (18.42 mm × 10.35 mm)
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT16863 are 18-bit noninverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The 'ABT16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16863 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16863 is characterized for operation from -40°C to 85°C.

The 'ABT16863 are 18-bit noninverting transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

The 'ABT16863 can be used as two 9-bit transceivers or one 18-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB\ or OEBA\) inputs.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16863 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16863 is characterized for operation from -40°C to 85°C.

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* データシート 18-Bit Bus Transceivers With 3-State Outputs データシート (Rev. C) 1997/05/01

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