ホーム ロジックと電圧変換 構成可能なプログラマブル ロジック IC コンフィギュラブル ゲート

SN74AUP1G99

アクティブ

3 ステート出力、低消費電力、ウルトラ コンフィギュラブル (大幅な再構成が可能) マルチファンクション ゲート

製品詳細

Technology family AUP Number of channels 1 Inputs per channel 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 Inputs per channel 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 5 pF Typ at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 7.4 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments.

  • Available in the Texas Instruments
    NanoFree™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 5 pF Typ at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 7.4 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).

The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).

The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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SN74AUC2G126 アクティブ 3 ステート出力、2 チャネル、0.8V ~ 2.7V ハイスピード バッファ Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G00 アクティブ 2 チャネル、2 入力、0.8V ~ 2.7V ハイスピード NAND ゲート Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G08 アクティブ 2 チャネル、2 入力、0.8V ~ 2.7V、超高速 (2.4ns)、AND ゲート Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74LVC1G99 アクティブ 3 ステート出力対応ウルトラ コンフィギュラブル マルチファンクション ゲート Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74AUC2G32 アクティブ 2 チャネル、2 入力、0.8V ~ 2.7V、超高速 (2.4ns)、OR ゲート Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G240 アクティブ 3 ステート出力、2 チャネル、0.8V ~ 2.7V ハイスピード インバータ Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G86 アクティブ 2 チャネル、2 入力、0.8V ~ 2.7V ハイスピード XOR (排他 OR) ゲート Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G125 アクティブ 3 ステート出力、2 チャネル、0.8V ~ 2.7V ハイスピード バッファ Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA

技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート Low-Power Ultra-Configurable Multiple-Function Gate With 3-State Outputs データシート (Rev. C) 2007/07/09
アプリケーション概要 シュミット トリガについて (Rev. B 翻訳版) PDF | HTML 英語版 (Rev.B) PDF | HTML 2025/05/08
アプリケーション概要 Utilizing Configurable Logic in System Design PDF | HTML 2024/10/30

設計と開発

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評価ボード

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シミュレーション・モデル

SN74AUP1G99 IBIS Model (Rev. A)

SCEM458 (458 KB) - IBIS モデル
サポート対象の製品とハードウェア
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian

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