SN74LV161284

アクティブ

19 ビット バス・インターフェイス

製品詳細

Technology family LV-A Applications IEEE1284 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LV-A Applications IEEE1284 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)

  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.

ダウンロード 字幕付きのビデオを表示 ビデオ

お客様が関心を持ちそうな類似品

open-in-new 代替品と比較
比較対象デバイスと類似の機能
SN74LV8T245 アクティブ 3 ステート出力採用、単一電源電圧、オクタル変換トランシーバ Wider voltage range

技術資料

star =TI が選定したこの製品の主要ドキュメント
結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
4 をすべて表示
種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN74LV161284 データシート (Rev. C) 2002年 11月 4日
アプリケーション・ノート Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024年 5月 14日
セレクション・ガイド Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
アプリケーション・ノート Logic Solutions For IEEE Std 1284 1999年 6月 1日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

シミュレーション・モデル

HSPICE Model for SN74LV161284

SCEM531.ZIP (111 KB) - HSpice Model
シミュレーション・モデル

SN74LV161284 IBIS Model (Rev. A)

SCEM021A.ZIP (96 KB) - IBIS Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ