TMS320VC5409A
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- \xD7 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature
- Extended Addressing Mode for 8M \xD7 16-Bit Maximum Addressable External Program Space
- 32K x 16-Bit On-Chip RAM Composed of:
- Four Blocks of 8K \xD7 16-Bit On-Chip Dual-Access Program/Data RAM
- 16K \xD7 16-Bit On-Chip ROM Configured for Program Memory
- Enhanced External Parallel Interface (XIO2)
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source (1)
- One 16-Bit Timer
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- CLKOUT Off Control to Disable CLKOUT
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (2) (JTAG) Boundary Scan Logic
- 144-Pin Ball Grid Array (BGA) (GGU Suffix)
- 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
- 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
- 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
- 3.3-V I/O Supply Voltage (160 and 120 MIPS)
- 1.6-V Core Supply Voltage (160 MIPS)
- 1.5-V Core Supply Voltage (120 MIPS)
(1) The on-chip oscillator is not available on all 5409A devices. For applicable devices, see the TMS320VC5409A Digital Signal Processor Silicon Errata (literature number SPRZ186).
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x\x99 DSP Functional Overview (literature number SPRU307).
TMS320C54x, MicroStar BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5409A also includes the control mechanisms to manage interrupts,
![](/product-folders/content/dam/ticom/images/icons/illustrative-icons/resources/information-icon.png)
No design support from TI available
This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.
技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | TMS320VC5409A Fixed-Point Digital Signal Processor データシート (Rev. G) | 2008年 10月 13日 | |||
* | エラッタ | TMS320VC5409A MicroStar BGA Discontinued and Redesigned | 2020年 5月 21日 | |||
* | エラッタ | TMS320VC5409A DSP Silicon Errata (Rev. C) | 2003年 5月 9日 | |||
アプリケーション・ノート | TMS320VC5402A/VC5409A/VC5410A/VC5416 Bootloader (Rev. F) | 2006年 6月 27日 | ||||
ユーザー・ガイド | TMS320C54x Chip Support Library API Reference Guide (Rev. D) | 2003年 5月 5日 | ||||
ユーザー・ガイド | TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) | 2001年 3月 31日 | ||||
ユーザー・ガイド | TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) | 2001年 1月 31日 | ||||
ユーザー・ガイド | TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) | 2001年 1月 31日 | ||||
ユーザー・ガイド | TMS320C54x DSP Applications Guide Reference Set Volume 4 | 1996年 10月 1日 |
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
TMDSEMU560V2STM-U — XDS560™ ソフトウェア v2 システム・トレース USB デバッグ・プローブ
XDS560v2 は、XDS560™ ファミリのデバッグ・プローブの中で最高の性能を達成し、従来の JTAG 規格 (IEEE1149.1) と cJTAG (IEEE1149.7) の両方をサポートしています。シリアル・ワイヤ・デバッグ (SWD) をサポートしていないことに注意してください。
すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。
(...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
---|---|---|
LQFP (PGE) | 144 | Ultra Librarian |
NFBGA (GWS) | 144 | Ultra Librarian |
NFBGA (ZWS) | 144 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。