CD40194B

Name: CD40194B
Brand: TI
SKU: CD40194B
Price: 0.464 USD

활성

CMOS 4비트 양방향 범용 시프트 레지스터

지금 주문

데이터 시트

document-pdfAcrobat CD40194B TYPES datasheet (Rev. B) (영어)

CD40194B

활성

데이터 시트

지금 주문

제품 상세 정보

Configuration

Universal

Bits (#)

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

8.5

IOL (max) (mA)

4.2

IOH (max) (mA)

-4.2

Supply current (max) (µA)

3000

Features

Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Configuration

Universal

Bits (#)

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

8.5

IOL (max) (mA)

4.2

IOH (max) (mA)

-4.2

Supply current (max) (µA)

3000

Features

Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Medium-speed: f_CL = 12 MHz (typ.) @ V_DD = 10 V
Fully static operation
Synchronous parallel or serial operation
Asynchronous master reset
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
- Arithmetic unit bus registers
- Serial/parallel conversions
- General-purpose register for bus-organized systems
- General-purpose registers

NOT RECOMMENDED FOR NEW DESIGNS

Medium-speed: f_CL = 12 MHz (typ.) @ V_DD = 10 V
Fully static operation
Synchronous parallel or serial operation
Asynchronous master reset
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
- Arithmetic unit bus registers
- Serial/parallel conversions
- General-purpose register for bus-organized systems
- General-purpose registers

NOT RECOMMENDED FOR NEW DESIGNS

CD40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET\ input resets all stages and forces all outputs low.

The CD40194B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET\ input resets all stages and forces all outputs low.

The CD40194B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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