CD4517B-MIL
- Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V
- Clock frequency 12 MHz (typ.) at VDD = 10 V
- Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
- Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
- Three-state outputs
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
Time-delay circuits
Scratch-pad memories
General-purpose serial shift-register applications
CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the CD4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.
The CD4517B is supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | CMOS Dual 64-Stage Static Shift Register datasheet | 1998/11/21 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
User guide | Signal Switch Data Book (Rev. A) | 2003/11/14 | ||
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001/12/03 |
설계 및 개발
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
CDIP (J) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치