홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 시프트 레지스터
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
시프트 레지스터

CD54HC4094

활성

3상 출력을 지원하는 고속 CMOS 로직 8단계 시프트-및-저장 버스 레지스터

지금 주문하기
데이터 시트

CD54HC4094

활성
데이터 시트 지금 주문하기

제품 상세 정보

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.
filter 기타 시프트 레지스터 찾기
다운로드

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
1개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State datasheet (Rev. F) PDF | HTML 1998/11/24

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​