홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
홈
로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

CD74AC646

활성

3상 출력을 지원하는 8진 비인버팅 버스 트랜시버/레지스터

지금 주문
데이터 시트

CD74AC646

활성
데이터 시트 지금 주문

제품 상세 정보

Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -55 to 125
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Buffered inputs
  • Typical propagation delay:
    5.3 ns @ VCC = 5 V, TA = 25°C, CL = 50pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    - Fanout to 15 FAST* ICs
    - Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

*FAST is a Registered Trademark of Fairchild Semiconductor Corp.
  • Buffered inputs
  • Typical propagation delay:
    5.3 ns @ VCC = 5 V, TA = 25°C, CL = 50pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    - Fanout to 15 FAST* ICs
    - Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

*FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The RCA CD54/74AC646 and CD54/74AC648 and the CD54/74ACT646 and CD54/74ACT648 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC648 and CD54/74ACT648 have inverting outputs. The CD54/74AC646 and CD54/74ACT646 have non-inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Output Enable (OE\) and Direction (DIR) inputs control the transceiver functions. Data present at the high-impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE\) is LOW. In the high-impednace mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE\) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time.

The CD74AC/ACT646 and CD74AC/ACT648 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54/ACT646 and CD54AC/ACT648, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

The RCA CD54/74AC646 and CD54/74AC648 and the CD54/74ACT646 and CD54/74ACT648 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC648 and CD54/74ACT648 have inverting outputs. The CD54/74AC646 and CD54/74ACT646 have non-inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Output Enable (OE\) and Direction (DIR) inputs control the transceiver functions. Data present at the high-impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE\) is LOW. In the high-impednace mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE\) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time.

The CD74AC/ACT646 and CD74AC/ACT648 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54/ACT646 and CD54AC/ACT648, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.
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다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74HCS245 활성 3상 출력을 지원하는 슈미트 트리거 입력 8진 버스 트랜시버 Longer average propagation delay (12ns), lower average drive strength (7.8mA)

기술 자료

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1개 모두 보기
유형 직함 날짜
* Data sheet Octal-Bus Transceiver/Registers, 3-State datasheet 1998/12/03

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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