DAC38RF89
- 14-Bit resolution, 9-GSPS DAC with multimode operation
- 16-Bit, Dual-channel data mode
- Max input rate: 2.5-GSPS
- Wideband digital up-converter
- Interpolation: 1,2,4,6,8,10,12,16,18,20,24x
- 12-Bit, Dual-channel data mode
- Max input rate: 3.33-GSPS
- Wideband digital Up-converter
- Interpolation: 1,2,24x
- 8-Bit, Single-channel data mode
- Max input rate: 9-GSPS
- 16-Bit, Dual-channel data mode
- JESD204B interface
- Subclass 1 for multichip synchronization
- DAC38RF89: Maximum lane rate: 12.5 Gbps
- DAC38RF82: Maximum lane rate: 12.8 Gbps
- Differential output
- Supports DC coupling
- RF Full-scale output power (with 2:1 balun):
3 dBm at 2.14 GHz
- Internal PLL and VCO with bypass
- DAC38RF82: fC(VCO) = 5.9 or 8.9 GHz
- DAC38RF89: fC(VCO) = 5 or 7.5 GHz
- Power supplies: -1.8 V, 1.0 V, 1.8 V
- Package: 10 x 10 mm BGA, 0.8 mm pitch,
144-balls
The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs) that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9-GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82).
In dual channel operation, the input interface is capable of data rates up to 3.33 GSPS at 12-bits and 2.5 GSPS at 16-bits resolution without interpolation. When used as a complex baseband transmitter with interpolation modes from 2x to 24x, the DAC38RF82 or DAC38RF89 is capable of synthesizing wideband signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz bandwidth with 12-bit input resolution.
The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample rate and can synthesize wideband signals from 0 to 4.5 GHz.
An optional low jitter PLL/VCO simplifies the DAC clock generation by allowing use of a lower frequency reference clock. DAC38RF82 and DAC38RF89 support different VCO frequency ranges, summarized in Device Comparison Table.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation datasheet (Rev. D) | PDF | HTML | 2020/04/14 |
Application note | Impact of Power-Supply Noise on Phase Noise Performance of RF DACs | 2018/06/13 | ||
Application note | Eye Scan Testing with the DAC38RFxx | 2017/08/10 | ||
Application note | Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information | 2017/08/02 | ||
Application note | DAC38RF8x Test Modes | 2017/07/25 | ||
EVM User's guide | DAC38RF8xEVM User's Guide (Rev. A) | 2017/03/24 | ||
Design guide | Efficient Power Supply Scheme for RF-Sampling DAC Reference Design | 2016/08/22 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
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The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
지원되는 제품 및 하드웨어
제품
고속 DAC(>10 MSPS)
트랜스미터
리시버
고속 ADC(≥10 MSPS)
RF 샘플링 트랜시버
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
지원되는 제품 및 하드웨어
제품
고속 DAC(>10 MSPS)
트랜스미터
리시버
고속 ADC(≥10 MSPS)
초음파 AFE
RF 샘플링 트랜시버
하드웨어 개발
평가 보드
소프트웨어
지원 소프트웨어
SLAC722 — DAC38RF8x EVM GUI
지원되는 제품 및 하드웨어
제품
고속 DAC(>10 MSPS)
트랜스미터
하드웨어 개발
평가 보드
TIDA-01215 — RF 샘플링 DAC에서 스퍼 및 위상 잡음 최적화를 위한 전원 공급 장치 레퍼런스 디자인
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
FCCSP (AAV) | 144 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.