홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

SN54ALS174

활성

클리어를 지원하는 16진 D형 플립플롭

지금 주문하기
데이터 시트

SN54ALS174

활성
데이터 시트 지금 주문하기

제품 상세 정보

Number of channels 6 Technology family ALS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 75 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 19000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 6 Technology family ALS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 75 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 19000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CDIP (J) 16 135.3552 mm² (— mm × — mm) CFP (W) 16 69.319 mm² (— mm × — mm)
  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)
  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.
filter 기타 D형 플립플롭 찾기
다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
SN74HC174 활성 클리어를 지원하는 16진 D형 플립플롭 Voltage range 2V to 6V, average propagation delay 20ns, average drive strength 8mA
비교 대상 장치와 유사한 기능.
SN74AHCT174 활성 클리어를 지원하는 16진 D형 플립플롭 Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
2개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E) 2002. 5. 23
* SMD SN54ALS174 SMD 83019012A 2016. 6. 21

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