SN54ALS243A
- Two-Way Asynchronous Communication Between Data Buses
- pnp Inputs Reduce dc Loading
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These quadruple bus transceivers are designed for asynchronous
two-way communication between data buses. The control-function
implementation allows for maximum flexibility in timing. These
devices allow data transmission from the A bus to the B bus or from
the B bus to the A bus depending upon the logic levels at the
output-enable (OEBA and 
)
inputs. The output-enable inputs can be used to disable the device so
that the buses are effectively isolated.
The dual-enable configuration gives the quadruple bus transceivers
the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input
in this transceiver configuration. When both control inputs are
enabled and all other data sources to the two sets of bus lines are
at high impedance, both sets of bus lines (eight in all) retain their
states. The 4-bit codes appearing on the two sets of buses are
identical.
The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Quadruple Bus Transceivers With 3-State Outputs datasheet (Rev. B) | 1994/12/01 | |
| * | SMD | SN54ALS243A SMD 84013022A | 2016/06/21 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
| Application note | Live Insertion | 1996/10/01 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995/08/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| LCCC (FK) | 20 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치