홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

SN54F74

활성

클리어 및 프리셋을 지원하는 듀얼 양극 에지 트리거 D형 플립플롭

지금 주문하기
데이터 시트

SN54F74

활성
데이터 시트 지금 주문하기

제품 상세 정보

Number of channels 2 Technology family F Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family F Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 80 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 16000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
LCCC (FK) 20 79.0321 mm² (— mm × — mm) CFP (W) 14 58.023 mm² (— mm × — mm) CDIP (J) 14 130.4652 mm² (— mm × — mm)
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
  • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

 

 

The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

 

 

The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.
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다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능.
CD74HCT74 활성 설정 및 리셋을 지원하는 고속 CMOS 로직 듀얼 양극 에지 트리거 D 플립플롭 Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA
CD74ACT74 활성 설정 및 리셋을 지원하는 듀얼 양극 에지 트리거 D형 플립플롭 Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

기술 자료

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2개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. A) 1993. 10. 1
* SMD SN54F74 SMD 5962-97592 2016. 6. 21

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