SN54HC138
- Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Wide Operating Voltage Range (2 V to 6 V)
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Maximum ICC
- Typical tpd = 15 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1-µA Maximum
- Active Low Outputs ( Selected Output is Low)
- Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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기술 자료
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1개 모두 보기 | 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) | PDF | HTML | 2021/10/08 |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치