홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

SN54HC273-DIE

마지막 구매
지금 주문하기
데이터 시트

SN54HC273-DIE

마지막 구매
데이터 시트 지금 주문하기

제품 상세 정보

Technology family HC Input type CMOS Output type CMOS IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Operating temperature range (°C) 25 to 25 Rating Space
Technology family HC Input type CMOS Output type CMOS IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Operating temperature range (°C) 25 to 25 Rating Space
DIESALE (TD) — See data sheet
  • Wide Operating Voltage Range
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 12 ns
  • Low Input Current
  • Contain Eight Flip-Flops With
    Single-Rail Outputs
  • Direct Clear Input
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Wide Operating Voltage Range
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 12 ns
  • Low Input Current
  • Contain Eight Flip-Flops With
    Single-Rail Outputs
  • Direct Clear Input
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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* 데이터 시트 Rad-Tolerant Space Grade Die, Quadruple 2-Input Positive-AND Gate, SN54HC273-DIE datasheet 2013. 6. 3

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