SN54LS373-SP

활성

3상 출력을 지원하는 8진 D형 트랜스페어런스 래치

제품 상세 정보

Number of channels 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 35 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Space
Number of channels 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 35 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 40000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Space
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92
  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

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기술 자료

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유형 직함 날짜
* Data sheet Octal D-Type Transparent Latches And Edge-Triggered Flip-Flops datasheet (Rev. B) 2002/08/23
Application brief DLA Approved Optimizations for QML Products (Rev. B) PDF | HTML 2024/10/23
Selection guide TI Space Products (Rev. J) 2024/02/12
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 2023/08/31
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 2022/11/17
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 2022/10/19
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Designing with the SN54/74LS123 (Rev. A) 1997/03/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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