홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 래치
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치

SN74ABT16843

활성

3상 출력을 지원하는 18비트 버스 인터페이스 D형 래치

지금 주문
데이터시트

SN74ABT16843

활성
데이터시트 지금 주문

제품 상세 정보

Number of channels 18 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 85000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 18 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 85000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Impedance State During Power Up and Power Down
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Impedance State During Power Up and Power Down
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.

The 'ABT16843 18-bit bus-interface D-type latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The 'ABT16843 can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device provides true data at its outputs.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs are in the high-impedance state during power up and power down. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16843 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16843 is characterized for operation from -40°C to 85°C.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
74ACT16841 활성 3상 출력을 지원하는 20비트 버스 인터페이스 D형 래치 Longer propagation delay (8ns), lower average drive strength (24mA)

기술 문서

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모두 보기20
유형 직함 날짜
* Data sheet 18-Bit Bus-Interface D-Type Latches With 3-State Outputs datasheet (Rev. E) 1997/05/01
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004/02/16
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997/03/01
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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패키지 핀 다운로드
SSOP (DL) 56 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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