SN74ALS996
- 3-State I/O-Type Read-Back Inputs
- Bus-Structured Pinout
- T/C\ Determines True or Complementary Data at Q Outputs
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high
transition of the clock (CLK) input when the enable (
) input is low. Data can be read
back onto the data inputs by taking the read (
) input low, in addition to having
low. When EN\ is high, both the
read-back and write modes are disabled. Transitions on should only be made with CLK high
to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity
(T/C\) input. When T/C\ is high, Q is the same as is stored in the
flip-flops. When T/C\ is low, the output data is inverted. The Q
outputs can be placed in the high-impedance state by taking the
output-enable (
) input high.
does not
affect the internal operation of the register. Old data can be
retained or new data can be entered while the outputs are off.
A low level at the clear (
)
input resets the internal registers low. The clear function is
asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit D-Type Edge-Triggered Read-Back Latches datasheet (Rev. B) | 1995/01/01 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
| Application note | Live Insertion | 1996/10/01 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995/08/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| SOIC (DW) | 24 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치