홈 로직 및 전압 변환 버퍼, 드라이버 및 트랜시버 범용 트랜시버
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로직 및 전압 변환
버퍼, 드라이버 및 트랜시버
범용 트랜시버

SN74ALVCH162334

활성

3상 출력을 지원하는 16비트 범용 버스 드라이버

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SN74ALVCH162334

활성
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제품 상세 정보

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

Widebus, EPIC are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

Widebus, EPIC are trademarks of Texas Instruments.

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE)\ input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from –40°C to 85°C.
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기술 자료

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19개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet SN74ALVCH162334 datasheet (Rev. H) 2004/08/24
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025/11/13
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018/09/17
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002/08/01
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999/09/08
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998/08/03
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998/05/13
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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시뮬레이션 모델

SN74ALVCH162334 IBIS Model (Rev. A)

SCEM066A.ZIP (10 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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