SN74ALVCH16501

활성

3상 출력을 지원하는 18비트 범용 버스 트랜시버

지금 주문하기

데이터 시트

document-pdfAcrobat SN74ALVCH16501 datasheet (Rev. J) (영어)

SN74ALVCH16501

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Positive input clamp diode, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

18

IOL (max) (mA)

24

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Bus-hold, Positive input clamp diode, Ultra high speed (tpd <5ns)

Technology family

ALVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² (18.42 mm × 10.35 mm)

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

Member of the Texas Instruments Widebus™ Family
UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
Operates From 1.65 V to 3.6 V
Max t_pd of 3.9 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
Operates From 1.65 V to 3.6 V
Max t_pd of 3.9 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB and OEBA)\, latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA\ is active low).

To ensure the high-impedance state during power up or power down, OEBA\ should be tied to V_CC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB and OEBA)\, latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA\ is active low).

To ensure the high-impedance state during power up or power down, OEBA\ should be tied to V_CC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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SN74LVTH16501

활성

3상 출력을 지원하는 3.3V ABT 18비트 범용 버스 트랜시버 Voltage range 2.7V to 3.6V, average propagation delay 4.5ns, average drive strength 64mA

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2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	SN74ALVCH16501 datasheet (Rev. J)			2004. 8. 27
	애플리케이션 노트	An Overview of Bus-Hold Circuit and the Applications (Rev. B)			2018. 9. 17