SN74ALVCH16825
- Member of the Texas Instruments Widebus™ Family
- EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
Widebus, EPIC are trademarks of Texas Instruments.
This 18-bit buffer and line driver is designed for 1.65-V to 3.6-V VCC operation.
This SN74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as two 9-bit buffers or one 18-bit buffer. It provides true data.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.
The SN74ALVCH16825 is characterized for operation from &$150;40°C to 85°C.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN74ALVCH16825 datasheet (Rev. D) | 2004. 9. 2 | ||
| 애플리케이션 노트 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018. 9. 17 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SSOP (DL) | 56 | Ultra Librarian |
| TSSOP (DGG) | 56 | Ultra Librarian |