홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 래치
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치

SN74AUC16373

활성

3상 출력을 지원하는 16비트 트랜스페어런스 D형 래치

지금 주문하기
데이터 시트

SN74AUC16373

활성
데이터 시트 지금 주문하기

제품 상세 정보

Number of channels 16 Technology family AUC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family AUC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 9 IOH (max) (mA) -9 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Member of the Texas Instruments Widebus™ Family
  • Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub 1-V Operable
  • Max tpd of 2 ns at 1.8 V
  • Low Power Consumption, 20-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub 1-V Operable
  • Max tpd of 2 ns at 1.8 V
  • Low Power Consumption, 20-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 16-bit transparent D-type latch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 16-bit transparent D-type latch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
SN74AVC16373 활성 3상 출력을 지원하는 16비트 트랜스페어런스 D형 래치 Voltage range 0.9V to 3.6V, average propagation delay 2ns, average drive strength 12mA
SN74LVC16373 활성 3상 출력을 지원하는 16비트 트랜스페어런스 D형 래치 Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

기술 자료

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* 데이터 시트 SN74AUC16373 datasheet (Rev. C) 2002. 11. 1
애플리케이션 노트 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022. 12. 15

설계 및 개발

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시뮬레이션 모델

SN74AUC16373 IBIS Model

SCEM295.ZIP (72 KB) - IBIS 모델
지원되는 제품 및 하드웨어
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
TVSOP (DGV) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
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