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SN74AVCB164245-EP

활성

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SN74AVCB164245-EP

활성
데이터 시트 지금 주문하기

제품 상세 정보

Bits (#) 16 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.4 Vin (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Applications GPIO, JTAG, SPI, UART Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 9.1 Technology family AVC Supply current (max) (mA) 0.1 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Bits (#) 16 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.4 Vin (max) (V) 3.6 Vout (min) (V) 1.4 Vout (max) (V) 3.6 Applications GPIO, JTAG, SPI, UART Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 9.1 Technology family AVC Supply current (max) (mA) 0.1 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Member of the Texas Instruments Widebus Family
  • DOC Circuitry Dynamically Changes Output Impedance,
    Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With
    IOH and IOL of ±24 mA at 2.5-V
    VCC
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the
    High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over
    Full 1.4-V to 3.6-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 750-V Charged-Device Model (C101)
  • Member of the Texas Instruments Widebus Family
  • DOC Circuitry Dynamically Changes Output Impedance,
    Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With
    IOH and IOL of ±24 mA at 2.5-V
    VCC
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCB Voltage
  • If Either VCC Input Is at GND, Both Ports Are in the
    High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over
    Full 1.4-V to 3.6-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 750-V Charged-Device Model (C101)

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND, both ports are in the high-impedance state.
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7개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 SN74AVCB164245-EP 16-Bit Dual-Supply Bus Transceiver datasheet (Rev. A) 2013. 2. 12
* 방사능 및 안정성 보고서 CAVCB164245MDGGREP Reliability Report 2013. 4. 24
* VID SN74AVCB164245-EP VID V6213602 2016. 6. 21
애플리케이션 노트 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024. 10. 2
애플리케이션 노트 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024. 7. 12
애플리케이션 노트 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024. 7. 3
선택 가이드 Voltage Translation Buying Guide (Rev. A) 2021. 4. 15

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