SN74F74

활성

클리어 및 프리셋을 지원하는 듀얼 상승 에지 트리거 D형 플립플롭

지금 주문

데이터 시트

document-pdfAcrobat Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. A) (영어)

SN74F74

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

2

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

20

IOH (max) (mA)

-1

Supply current (max) (µA)

16000

Features

Very high speed (tpd 5-10ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Number of channels

2

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

100

IOL (max) (mA)

20

IOH (max) (mA)

-1

Supply current (max) (µA)

16000

Features

Very high speed (tpd 5-10ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

SOP (NS)

14

79.56 mm² 10.2 x 7.8

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

The output levels are not guaranteed to meet the minimum levels for V_OH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.

These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.

The output levels are not guaranteed to meet the minimum levels for V_OH. Furthermore, this configuration is nonstable; that is, it will not persist when or returns to its inactive (high) level.

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