SN74HCT623
- Operating Voltage Range of 4.5 V to 5.5 V
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 11 ns
- ±6-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Inputs Are TTL-Voltage Compatible
- Lock Bus-Latch Capability
- True Logic
- High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing.
The HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA\) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA\ are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN54HCT623, SN74HCT623 datasheet (Rev. C) | 2003/03/18 | |
Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
User guide | Signal Switch Data Book (Rev. A) | 2003/11/14 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997/06/01 | ||
Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
Application note | SN54/74HCT CMOS Logic Family Applications and Restrictions | 1996/05/01 | ||
Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996/04/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | 다운로드 |
---|---|---|
PDIP (N) | 20 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치