SN74LS174

Name: SN74LS174
Brand: TI
SKU: SN74LS174
Price: 0.399 USD

활성

클리어를 지원하는 16진 D형 플립플롭

지금 주문하기

데이터 시트

document-pdfAcrobat Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. A) (영어)

SN74LS174

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of channels

6

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

35

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

26000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Number of channels

6

Technology family

LS

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

35

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

26000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

0 to 70

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

'174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
'175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
Three Performance Ranges Offered: See Table Lower Right
Buffered Clock and Direct Clear Inputs
Individual Data Input to Each Flip-Flop
Applications include:

Buffer/Storage Registers
Shift Registers
Pattern Generators

'174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
'175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
Three Performance Ranges Offered: See Table Lower Right
Buffered Clock and Direct Clear Inputs
Individual Data Input to Each Flip-Flop
Applications include:

Buffer/Storage Registers
Shift Registers
Pattern Generators

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

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