SN74LV165B-EP
- 2 V to 5.5 V V CC operation
- Maximum t pd of 10.5 ns at 5 V
- Supports mixed-mode voltage operation on all ports
- I off supports partial-power-down mode operation
- Latch-up performance exceeds 250 mA per JESD 17
- Operating ambient temperature: -55°C to +125°C
- Supports defense, aerospace, and medical applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
The SN74LV165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V CC operation.
When the device is clocked, data is shifted toward the serial output Q H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165B-EP devices features a clock-inhibit function and a complemented serial output, Q H.
This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 | |
|---|---|---|---|---|---|---|
| * | 데이터 시트 | SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise,Parallel-Load 8-Bit Shift Registers datasheet (Rev. A) | PDF | HTML | 2023. 8. 23 |
설계 및 개발
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14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |