SN74LVC16244A
- Member of the Texas Instruments
Widebus Family - Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.1 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Supports Mixed-Mode Signal Operation on All Ports
(5-V Input/Output Voltage With 3.3-V VCC) - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74LVC16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LVC16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN74LVC16244A 16-Bit Buffer/Driver With 3-State Outputs datasheet (Rev. C) | PDF | HTML | 2014. 1. 28 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SSOP (DL) | 48 | Ultra Librarian |
| TVSOP (DGV) | 48 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |