SN74LVC1G132
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Available in Texas Instruments
NanoStar™ and NanoFree™ Packages - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.3 ns at 3.3 V
- Low Power Consumption, 10-µA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.
Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 | |
|---|---|---|---|---|---|---|
| * | 데이터 시트 | SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D) | PDF | HTML | 2017. 6. 8 |
설계 및 개발
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5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |