TMS320C6746

활성

저전력 C674x 부동 소수점 DSP - 456MHz

지금 주문하기

데이터 시트

document-pdfAcrobat TMS320C6746 Fixed- and Floating-Point DSP datasheet (Rev. F) (영어) PDF | HTML

사용자 가이드

document-pdfAcrobat
TMS320C6746 DSP Technical Reference Manual (Rev. C) (영어)

TMS320C6746

활성

데이터 시트

지금 주문하기

제품 상세 정보

CPU

32-/64-bit

Frequency (MHz)

375, 456

Display type

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Security

Secure boot

Rating

Catalog

Operating temperature range (°C)

-40 to 105

CPU

32-/64-bit

Frequency (MHz)

375, 456

Display type

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Security

Secure boot

Rating

Catalog

Operating temperature range (°C)

-40 to 105

NFBGA (ZWT)

361

256 mm² (16 mm × 16 mm)

NFBGA (ZCE)

361

169 mm² (13 mm × 13 mm)

375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2746 MFLOPS
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core
- Load-Store Architecture With Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units:
  - Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    - 2 SP × SP → SP Per Clock
    - 2 SP × SP → DP Every Two Clocks
    - 2 SP × DP → DP Every Three Clocks
    - 2 DP × DP → DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
Software Support
- TI DSPBIOS
- Chip Support Library and DSP Library
1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following:
  - 16-Bit DDR2 SDRAM With 256-MB Address Space
  - 16-Bit mDDR SDRAM With 256-MB Address Space
Three Configurable 16550-Type UART Modules:
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
Two Master and Slave Inter-Integrated Circuits
(I²C Bus™)
One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM Per Core
  - 512 Bytes of Data RAM Per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 2.0 OTG Port With Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
Two Multichannel Buffered Serial Ports (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
Video Port Interface (VPIF):
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
Universal Parallel Port (uPP):
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Packages:
- 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
- 361-Ball Pb-Free PBGA [ZWT Suffix],
  0.80-mm Ball Pitch
Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2746 MFLOPS
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Channel Controllers
- 3 Transfer Controllers
- 64 Independent DMA Channels
- 16 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core
- Load-Store Architecture With Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units:
  - Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    - 2 SP × SP → SP Per Clock
    - 2 SP × SP → DP Every Two Clocks
    - 2 SP × DP → DP Every Three Clocks
    - 2 DP × DP → DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
Software Support
- TI DSPBIOS
- Chip Support Library and DSP Library
1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM With 128-MB Address Space
- DDR2/Mobile DDR Memory Controller With one of the Following:
  - 16-Bit DDR2 SDRAM With 256-MB Address Space
  - 16-Bit mDDR SDRAM With 256-MB Address Space
Three Configurable 16550-Type UART Modules:
- With Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
Two Master and Slave Inter-Integrated Circuits
(I²C Bus™)
One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM Per Core
  - 512 Bytes of Data RAM Per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 2.0 OTG Port With Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
One Multichannel Audio Serial Port (McASP):
- Two Clock Zones and 16 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable
- FIFO Buffers for Transmit and Receive
Two Multichannel Buffered Serial Ports (McBSPs):
- Supports TDM, I2S, and Similar Formats
- AC97 Audio Codec Interface
- Telecom Interfaces (ST-Bus, H100)
- 128-Channel TDM
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant
- MII Media-Independent Interface
- RMII Reduced Media-Independent Interface
- Management Data I/O (MDIO) Module
Video Port Interface (VPIF):
- Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
- Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
Universal Parallel Port (uPP):
- High-Speed Parallel Interface to FPGAs and Data Converters
- Data Width on Both Channels is 8- to 16-Bit Inclusive
- Single-Data Rate or Dual-Data Rate Transfers
- Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
- 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Timestamps
Packages:
- 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
- 361-Ball Pb-Free PBGA [ZWT Suffix],
  0.80-mm Ball Pitch
Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

The TMS320C6746 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The DSP L2 is accessible by other hosts in the system.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; two I²C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

A video port interface (VPIF) provides a flexible video I/O port.

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38개 모두 보기

상위 문서	유형	직함	형식 옵션	날짜
*	데이터 시트	TMS320C6746 Fixed- and Floating-Point DSP datasheet (Rev. F)	PDF \| HTML	2017. 1. 31
*	사용 설명서	TMS320C6746 DSP Technical Reference Manual (Rev. C)		2016. 9. 12
*	정오표	TMS320C6746 Fixed- and Floating-Point DSP (Revs 2.3, 2.1, 2.0, 1.1 & 1.0) (Rev. H)		2014. 3. 21
	애플리케이션 노트	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021. 5. 19
	애플리케이션 노트	OMAPL138/C6748 ROM Bootloader Resources and FAQ (Rev. A)	PDF \| HTML	2021. 1. 21
	사용 설명서	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020. 6. 1
	애플리케이션 노트	Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x		2019. 12. 20
	사용 설명서	L138/C6748 development kit (LCDK) (Rev. A)	PDF \| HTML	2019. 9. 18
	애플리케이션 노트	Using DSPLIB FFT Implementation for Real Input and Without Data Scaling	PDF \| HTML	2019. 6. 11
	애플리케이션 노트	Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx	PDF \| HTML	2019. 4. 25
	애플리케이션 노트	TMS320C6748/46/42 power consumption summary	PDF \| HTML	2019. 3. 26
	애플리케이션 노트	General Hardware Design/BGA PCB Design/BGA	PDF \| HTML	2019. 2. 22
	애플리케이션 노트	OMAP-L13x / C674x / AM1x schematic review guidelines	PDF \| HTML	2019. 2. 14
	애플리케이션 노트	McASP Design Guide - Tips, Tricks, and Practical Examples		2019. 1. 10
	사용 설명서	PRU Assembly Instruction User Guide		2018. 2. 16
	애플리케이션 노트	Processor SDK RTOS Audio Benchmark Starter Kit		2017. 4. 12
	애플리케이션 노트	TI DSP Benchmarking	PDF \| HTML	2016. 1. 13
	애플리케이션 노트	Using the TMS320C6748/C6746/C6742 Bootloader (Rev. F)		2014. 1. 23
	사용 설명서	System Analyzer User's Guide (Rev. F)		2013. 11. 18
	애플리케이션 노트	OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility (Rev. B)		2013. 9. 27
	애플리케이션 노트	Powering the TMS320C6742, TMS320C6746, and TMS320C6748 With the TPS650061		2011. 12. 19
	애플리케이션 노트	Introduction to TMS320C6000 DSP Optimization		2011. 10. 6
	사용 설명서	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		2011. 9. 14
	애플리케이션 노트	Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B)		2011. 8. 29
	애플리케이션 노트	Simple Power Solution Using LDOs (Rev. B)		2011. 8. 29
	애플리케이션 노트	High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C)		2011. 8. 29
	백서	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		2011. 5. 19
	사용 설명서	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		2010. 8. 3
	사용 설명서	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		2010. 7. 30
	애플리케이션 노트	High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A)		2010. 5. 5
	애플리케이션 노트	High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A)		2010. 5. 5
	사용 설명서	OMAP-L138/C6748/C6746 Programmable Real-Time Unit Subsystem		2009. 8. 24
	애플리케이션 노트	TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing		2009. 8. 17
	애플리케이션 노트	TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing		2009. 8. 17
	애플리케이션 노트	TMS320C6748/46/42 Complementary Products		2009. 7. 20
	백서	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		2009. 6. 24
	애플리케이션 노트	TMS320C674x/OMAP-L1x USB Compliance Checklist		2009. 3. 12
	사용 설명서	TMS320C674x DSP Cache User's Guide (Rev. A)		2009. 2. 11

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TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

XDS200은 TI 20핀 커넥터(TI 14핀, (...)

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TMDSEMU560V2STM-U — XDS560™ 소프트웨어 v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(임베디드 추적 버퍼)가 있는 모든 ARM 및 DSP 프로세서에서 코어와 시스템 트레이스를 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, TI 20핀 및 ARM (...)

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TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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LB-3P-TRACE32-DSP — DSP(디지털 신호 프로세서)용 Lauterbach TRACE32 디버그 및 트레이스 시스템

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

발송: Lauterbach GmbH

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PROCESSOR-SDK-C6748 — C6748 프로세서용 프로세서 SDK TI-RTOS 지원

프로세서 SDK(소프트웨어 개발 키트)는 TI 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로, 이를 통해 벤치마크와 데모를 손쉽게 설정하고 빠르고 간편하게 액세스할 수 있습니다. 프로세서 SDK의 모든 릴리스는 TI의 광범위한 포트폴리오 내에서 일관되므로 개발자는 디바이스간에 소프트웨어를 자유롭게 재사용하고 마이그레이션할 수 있습니다. 프로세서 SDK와 TI의 임베디드 프로세서 솔루션을 사용하면 그 어느 때보다 쉽게 확장 가능한 플랫폼 솔루션을 개발할 수 있습니다.

C6748, C6746 및 C6742용 프로세서 (...)

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PROCESSOR-SDK-RTOS-OMAPL138 — TI-RTOS Processor SDK for OMAP-L138, OMAP-L132 and C6748, C6746, C6742 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

프로세서 SDK에는 Linux 및 TI-RTOS 운영 (...)

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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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MATHLIB — 부동 소수점 디바이스용 DSP 수학 라이브러리

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)

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SPRC264 — TMS320C5000/6000 IMGLIB(이미지 라이브러리)

C5000/6000 이미지 처리 라이브러리(IMGLIB)는 C 프로그래머를 위한 최적화된 이미지/비디오 처리 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 이미지/비디오 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. IMGLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.

벤치마크 확인: DSP 코어 벤치마크

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SPRC265 — TMS320C6000 DSP 라이브러리(DSPLIB)

TMS320C6000 DSPLIB(디지털 신호 프로세서 라이브러리)는 C 프로그래머를 위한 플랫폼에 최적화된 DSP 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 신호 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. DSPLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.

벤치마크 확인: DSP 코어 벤치마크

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TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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소프트웨어 코덱

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VoIP, 음성 및 오디오 코덱

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

발송: Adaptive Digital Technologies, Inc.

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