UCD7100
- Adjustable current limit protection
- 3.3-V, 10-mA internal regulator
- DSP/µC compatible inputs
- Single ±4-A TrueDrive™high current driver
- 10-ns typical rise and fall times with 2.2-nF loads
- 25-ns input-to-output propagation delay
- 25-ns current sense to output delay
- Programmable current limit threshold
- Digital output current limit flag
- 4.5-V to 15-V supply voltage range
- Rated from –40°C to 105°C
- Lead(Pb)-free packaging
The UCD7100 device is part of the UCD7K family of digital control compatible drivers for applications that use digital control technology that requires fast local peak current limit protection.
The UCD7100 is a low-side ±4-A high-current MOSFET gate driver. It allows the digital power controllers such as UCD9110 or UCD9501 to interface to the power stage in single ended topologies. It provides a cycle-by-cycle current limit function with programmable threshold and a digital output current limit flag which can be monitored by the host controller. With a fast 25-ns cycle-by-cycle current limit protection, the driver can turn off the power stage in the unlikely event that the digital system can not respond to a failure situation in time.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | UCD7100 Digital Control Compatible Single Low-Side ±4-A MOSFET Driver with Current Sense datasheet (Rev. E) | PDF | HTML | 2021. 11. 8 | |
| 애플리케이션 노트 | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024. 1. 22 | ||
| 애플리케이션 노트 | Using a Single-Output Gate-Driver for High-Side or Low-Side Drive (Rev. B) | PDF | HTML | 2023. 9. 8 | ||
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020. 2. 28 | |||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020. 2. 28 | |||
| Application brief | How to overcome negative voltage transients on low-side gate drivers' inputs | 2019. 1. 18 | |||
| 선택 가이드 | Power Management Guide 2018 (Rev. R) | 2018. 6. 25 | |||
| Application brief | Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole | 2018. 3. 16 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTSSOP (PWP) | 14 | Ultra Librarian |
주문 및 품질
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