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TMS320C40

NOT RECOMMENDED FOR NEW DESIGNS

Digital Signal Processors

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Data sheet
TMS320C40 is not recommended for new designs
Although this product continues to be in production to support previous designs, we don't recommend it for new designs. Consider one of these alternates:
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Similar functionality to the compared device
TMS320C6747 ACTIVE Low power C674x floating-point DSP- 456MHz, PBGA This product is a newer generation of floating point DSPs with higher performance & improved connectivity options.

TMS320C40

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

DSP (max) (MHz) 50, 60 Rating Military Operating temperature range (°C) to
DSP (max) (MHz) 50, 60 Rating Military Operating temperature range (°C) to
CPGA (GF) 325 2232.5625 mm² 47.25 x 47.25
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • '320C40-60:
      33-ns Instruction Cycle Time,
      330 MOPS, 60 MFLOPS,
      30 MIPS, 384M Bytes/s
    • '320C40-50:
      40-ns Instruction Cycle Time
    • '320C40-40:
      50-ns Instruction Cycle Time
  • Six Communications Ports
  • Six-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
  • Single Cycle, 1/x, 1/
  • Source-Code Compatible With TMS320C3x
  • Single-Cycle 40-Bit Floating-Point,
    32-Bit Integer Multipliers
  • Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
  • IEEE 1149.1 (JTAG) Boundary Scan Compatible
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-Bus, Data-Bus, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • 325-Pin Ceramic Grid Array (GF Suffix)
  • Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
  • Software-Communication-Port Reset
  • NMI\ With Bus-Grant Feature
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
  • IDLE2 Clock-Stop Power-Down Mode
  • 5-V Operation

    IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture
    EPIC and TI are trademarks of Texas Instruments Incorporated.
  • Highest Performance Floating-Point Digital Signal Processor (DSP)
    • '320C40-60:
      33-ns Instruction Cycle Time,
      330 MOPS, 60 MFLOPS,
      30 MIPS, 384M Bytes/s
    • '320C40-50:
      40-ns Instruction Cycle Time
    • '320C40-40:
      50-ns Instruction Cycle Time
  • Six Communications Ports
  • Six-Channel Direct Memory Access (DMA) Coprocessor
  • Single-Cycle Conversion to and From IEEE-754 Floating-Point Format
  • Single Cycle, 1/x, 1/
  • Source-Code Compatible With TMS320C3x
  • Single-Cycle 40-Bit Floating-Point,
    32-Bit Integer Multipliers
  • Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers
  • IEEE 1149.1 (JTAG) Boundary Scan Compatible
  • Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
    • High Port-Data Rate of 120M Bytes/s ('C40-60) (Each Bus)
    • 16G-Byte Continuous Program/Data/Peripheral Address Space
    • Memory-Access Request for Fast, Intelligent Bus Arbitration
    • Separate Address-Bus, Data-Bus, and Control-Enable Pins
    • Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
  • 325-Pin Ceramic Grid Array (GF Suffix)
  • Fabricated Using 0.72-um Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
  • Software-Communication-Port Reset
  • NMI\ With Bus-Grant Feature
  • Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
  • On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
    • 512-Byte Instruction Cache
    • 8K Bytes of Single-Cycle Dual-Access Program or Data RAM
    • ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports
  • IDLE2 Clock-Stop Power-Down Mode
  • 5-V Operation

    IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary-Scan Architecture
    EPIC and TI are trademarks of Texas Instruments Incorporated.

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.

The '320C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The '320C40 is a part of the fourth generation of DSPs from Texas Instruments and is designed primarily for parallel processing.
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Technical documentation

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Type Title Date
* Data sheet Digital Signal Processor datasheet 01 Jan 1996
Application note 320C3x, 320C4x, and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D) 06 Aug 2004
User guide TMS320C3x/C4x Assembly Language Tools User's Guide (Rev. D) 16 Apr 1998
User guide TMS320C3x/C4x Optimizing C Compiler User's Guide (Rev. H) 14 Apr 1998
Application note Implementing Continuously Programmable Digital Filters w/ TMS320C30/40 DSP (Rev. A) 01 Aug 1997
Application note Predator: A Posture Tracking System 01 Aug 1997
Application note A Hardware Monitor Using TMS320C40 Analysis Module & JTAG for Perf Measurements 01 Jul 1997
Application note Creating an Interactive Simulation Environment Using TMS320C40 Multi-DSP System 01 Jul 1997
Application note Digital Monopulse Doppler Radar and DSP Teaching 01 Jul 1997
Application note EDRAM Controller for the 60MHz TMS320C40 DSP 01 Jul 1997
Application note Implementing a Digital Tracker for Monopulse Radar Using the TMS320C40 DSP 01 Jul 1997
Application note Implementing a Real-Time Application on a TMS320C40 Multi-DSP 01 Jul 1997
Application note A Novel Way of Using TMS320C40 Cache 01 Jun 1997
Application note A Simple Way to Terminate Unused TMS320C40 Comm Ports 01 Jun 1997
Application note Designing With TMS320C40 Comm Ports: Part 1 01 Jun 1997
Application note Fast Logarithms on a Floating-Point Device 01 Jun 1997
Application note TMS320C40 Boot Loader Selection 01 Jun 1997
Application note TMS320C40 DMA Memory Transfer Timing 01 Jun 1997
Application note TMS320C40 Emulator TIPs 01 Jun 1997
Application note Video Restoration on a Multiple TMS320C40 System 01 Nov 1996
Application note Design of Active Noise Control Systems With the TMS320 Family 01 Jun 1996
User guide JTAG/MPSD Emulation Technical Reference (Rev. A) 01 Dec 1994
Application note Setting Up TMS320 DSP Interrupts in 'C' 01 Nov 1994
User guide TMS320C4x Parallel Runtime Support Library User's Guide (Rev. A) 01 Oct 1994
User guide TMS320C4x Parallel Processing Development System Technical Reference (Rev. A) 08 Apr 1994
Application note Parallel 2-D FFT Implementation With TMS320C4x DSPs (Rev. A) 01 Feb 1994
Application note Parallel Digital Signal Processing With the TMS320C40 01 Feb 1994
Application note Parallel Processing With TMS320C4x 01 Feb 1994
Application note Prototyping the TI TMS320C40 to the Cypress VIC068/VAC068 VME Interface 01 Feb 1994
Application note Transmission of Still and Moving Images Over Narrowband Channels 01 Feb 1994
Application note Calculation of TMS320C40 Power Dissipation 01 Nov 1993
User guide Parallel Debug Mgr Addendum to TMS320C4x & TMS320C5x C Source Debugger UGs 01 Apr 1993
User guide TMS320C4x C Source Debugger User's Guide 01 May 1992

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Support software

TMDS3240130SP2 — Download TMS320C3x/C4x Code Composer v4.1 Service Pack 2

Additional Information


Code Composer v4 was the last release of the Code Composer IDE that supported older digital signal processors such as TMS320C3x/4x and TMS320C2x/C5x.  There were different versions for these families. These products are no longer available for purchase or download. (...)

Supported products & hardware

Supported products & hardware

Products
Digital signal processors (DSPs)
TMS320C40 — Digital Signal Processors
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Simulation model

C40 GFL BSDL Model

SPRM168.ZIP (6 KB) - BSDL Model
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TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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