74AC11138
- Designed specifically for high-speed memory decoders and data transmission systems
- Incorporates three enable inputs to simplify cascading and/or data reception
- Center-Pin VCC and GND configurations minimize high-speed switching noise
- EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm process
- 500-mA typical latch-up immunity at 125 °C
- Package options include plastic small-outline (D) and thin shrink small-outline (PW) packages, and standard plastic 300-mil DIPs (N)
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.
技術文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1 類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 74AC11138 3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. C) | PDF | HTML | 2024年 5月 22日 |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點