ADC08DJ5200RF
- ADC core:
- 8-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS = 1
VPP-DIFF):
- Dual-channel mode: –143.4dBFS/Hz
- Single-channel mode: –146.2dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz, TYP): 7.8 Bits
- Noise floor (–20dBFS, VFS = 1
VPP-DIFF):
- Buffered analog inputs with VCMI of
0V:
- Analog input bandwidth (–3dB): 8.1GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 3.8W
- Power supplies: 1.1V, 1.9V
The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC08DJ5200RF 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) | PDF | HTML | 2025/4/8 | ||
| 應用說明 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025/3/28 | |||
| 應用說明 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025/3/26 |
設計與開發
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ADC08DJ5200RFEVM — 具有雙路 5.2 GSPS 或單路 GSPS-10.4 且適用於射頻取樣 8 位元 ADC 的 ADC08DJ5200RF 評估模組
ADC08DJ5200RF 評估模組 (EVM) 是用於評估 ADC08DJ5200RF 的平台。ADC08DJ5200RF 是一款低功耗、8 位元、雙通道 5.2-GSPS 或單通道 10.4-GSPS 的射頻取樣類比轉數位轉換器 (ADC)，具有緩衝類比輸入、整合式數位降壓轉換器與 JESD204B/C 介面。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。
ADC08DJ5200RFEVM 隨附 LMX2594 時脈合成器和 LMK04828 JESD204B/C 時脈產生器，可配置成提供適何完整 JESD204B/C 子類別 1 時脈解決方案的超低抖動 ADC (...)
TI204C-IP — Request for JESD204 rapid design IP
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JESD204 快速設計 IP 無需權利金，用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結，針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後，透過安全下載連結提供 IP。
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ADC12DJ5200RF-CALC — ADC12DJ5200RF 輸入網路全刻度計算工具。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |