CD74HC4017-EP

Name: CD74HC4017-EP
Brand: TI
SKU: CD74HC4017-EP
Price: 1.126 USD

現行

具有 10 個解碼輸出的增強型產品十進位計數器/分頻器

立即訂購

產品規格表

document-pdfAcrobat CD74HC4017-EP datasheet (英文)

CD74HC4017-EP

現行

產品規格表

立即訂購

產品詳細資料

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

HiRel Enhanced Product

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

HiRel Enhanced Product

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of –40°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_max = 60 MHz at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
V_CC Voltage = 2 V to 6 V
High Noise Immunity N_IL or N_IH = 30% of V_CC, V_CC = 5 V

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of –40°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_max = 60 MHz at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
V_CC Voltage = 2 V to 6 V
High Noise Immunity N_IL or N_IH = 30% of V_CC, V_CC = 5 V

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

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