CDC319

現行

具有 I2C 控制介面的 1 線路到 10 線路時鐘驅動器

立即訂購

產品規格表

document-pdfAcrobat 1-Line To 10-Line Clock Driver datasheet (Rev. A) (英文)

CDC319

現行

產品規格表

立即訂購

產品詳細資料

Function

Single-ended

Output frequency (max) (MHz)

100

Number of outputs

10

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

250

Features

I2C interface

Operating temperature range (°C)

0 to 70

Rating

Catalog

Output type

LVTTL

Input type

LVTTL

Function

Single-ended

Output frequency (max) (MHz)

100

Number of outputs

10

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

250

Features

I2C interface

Operating temperature range (°C)

0 to 70

Rating

Catalog

Output type

LVTTL

Input type

LVTTL

SSOP (DB)

28

79.56 mm² 10.2 x 7.8

High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications
Output Skew, t_sk(o), Less Than 250 ps
Pulse Skew, t_sk(p), Less Than 500 ps
Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules)
I²C Serial Interface Provides Individual Enable Control for Each Output
Operates at 3.3 V
Distributed V_CC and Ground Pins Reduce Switching Noise
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Packaged in 28-Pin Shrink Small Outline (DB) Package

High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications
Output Skew, t_sk(o), Less Than 250 ps
Pulse Skew, t_sk(p), Less Than 500 ps
Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules)
I²C Serial Interface Provides Individual Enable Control for Each Output
Operates at 3.3 V
Distributed V_CC and Ground Pins Reduce Switching Noise
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Packaged in 28-Pin Shrink Small Outline (DB) Package

The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C.

The device provides a standard mode (100K-bits/s) I²C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I²C device address table. Both of the I²C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 k) and are 5-V tolerant.

Three 8-bit I²C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported).

The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.

The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C.

The device provides a standard mode (100K-bits/s) I²C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I²C device address table. Both of the I²C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 k) and are 5-V tolerant.

Three 8-bit I²C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported).

The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.

filter

尋找其它時鐘緩衝器

下載觀看有字幕稿的影片影片

技術文件

star

=TI 所選的此產品重要文件

找不到結果。請清除您的搜尋條件，然後再試一次。

檢視所有 1

	類型	標題		日期
*	Data sheet	1-Line To 10-Line Clock Driver datasheet (Rev. A)		2001年 10月 25日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDC319 IBIS Model

SCAC011.ZIP (8 KB) - IBIS Model

下載

模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

要求

封裝	針腳	CAD 符號、佔位空間與 3D 模型
SSOP (DB)	28	Ultra Librarian

適用 TI 的評估品項標準條款與條件。

CDC319

具有 I2C 控制介面的 1 線路到 10 線路時鐘驅動器

CDC319

產品詳細資料

技術文件

設計與開發

CDC319 IBIS Model

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

影片系列

影片