CDCE421A
- Single Supply at 3.3 V for LVPECL or LVDS Operation
- High-Performance Clock Multiplier, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer
- Low Output Jitter: 380 fs RMS typical (from 10 kHz to 20 MHz)
- Low Phase Noise at High Frequency (708-MHz LVPECL):
- Typically -109 dBc/Hz at 10 kHz and -146dBc/Hz at 10 MHz from the carrier
- Supports Crystal or LVCMOS Input Frequencies from 27.35 MHz to 38.33 MHz
- Output Frequency Ranges from 10.9 MHz to 766.7 MHz and from 875.2 MHz to 1175 MHz
- Low-Voltage Differential Signaling (LVDS) Output, 100-
Differential Off-Chip Termination, 10.9-MHz to 400-MHz Frequency Range - Differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) Outputs, 10.9-MHz to 1.175-GHz Frequency Range
- Two Fully-Integrated Voltage-Controlled Oscillators (VCO) Support Wide Output Frequency Range
- Fully Integrated Programmable Loop Filter
- Typical Power Consumption at 3.3 V:
- 274 mW in LVDS mode
- 250 mW in LVPECL mode
- Chip Enable Control Pin
- Simple Serial Interface Allows Programming after Manufacturing
- Integrated On-Chip Nonvolatile Memory (EEPROM) Stores Settings Without Applying High Voltage
- Available in 4-mm × 4-mm QFN-24 Package
- ESD Protection Exceeds 2 kV (HBM)
- Industrial Temperature Range: -40°C to +85°C
- APPLICATIONS
- Low-Cost, High-Frequency Crystal Oscillator
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The CDCE421A is a high-performance, low phase noise clock generator. It has two fully-integrated, low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range. It also features an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the phase-locked loop (PLL) based frequency synthesizer.
The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL). The prescaler divider, feedback divider, output divider, and VCO selection set the output frequency with respect to fXTAL.
In the CDCE421A, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider should be between 60 and 64 as shown in to maintain a stable control loop.
The CDCE421A supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a proprietary simple serial interface (SSI).
The device operates in 3.3-V supply environment for both LVPECL and LVDS outputs and is characterized for operation from -40°C to +85°C. The CDCE421A is available in a QFN-24 4-mm × 4-mm package.
CDCE421 Users:The CDCE421A provides several device enhancements to the CDCE421.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE421A datasheet | 2009年 4月 21日 | |
| EVM User's guide | CDCE421AEVM User Guide | 2009年 6月 2日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 引腳 | 下載 |
|---|---|---|
| VQFN (RGE) | 24 | 檢視選項 |
| WAFERSALE (YS) | — |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
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