CDCE937-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C4B
- In-System Programmability and EEPROM
- Serial Programmable Volatile Register
- Nonvolatile EEPROM to Store Customer Setting
- Flexible Input Clocking Concept
- External Crystal: 8MHz to 32MHz
- On-Chip VCXO: Pull Range ±150ppm
- Single-Ended LVCMOS up to 160MHz
- Free Selectable Output Frequency up to 230 MHz
- Low-Noise PLL Core
- Integrated PLL Loop Filter Components
- Low Period Jitter (Typical 60ps)
- Separate Output Supply Pins
- CDCE937-Q1: 3.3V and 2.5V
- CDCEL937-Q1: 1.8V
- Flexible Clock Driver
- Three User-Definable Control Inputs [S0/S1/S2]; for Example: SSC Selection, Frequency Switching, Output Enable, or Power Down
- Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS
- Generates Common Clock Frequencies Used With TI- DaVinci™, OMAP™, DSPs
- Programmable SSC Modulation
- Enables 0PPM Clock Generation
- 1.8V Device Power Supply
- Wide Temperature Range –40°C to 125°C
- Packaged in TSSOP
- Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
The CDCE937-Q1 and CDCEL937-Q1 devices are modular, phase-locked loop (PLL)-based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx937-Q1 to the necessary specifications.
The CDCEx937-Q1 generates up to seven output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS, as these platforms are evolving into smaller and more cost effective systems.
Furthermore, each output can be programmed in-system for any clock frequency up to 230MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25.
Customization of frequency programming and SSC are accessed using three user-defined control pins. This eliminates the additional interface requirement to control the clock. Specific power-up and power-down sequences can also be defined to the user’s needs.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCEx937-Q1 Programmable 3-PLL VCXO Clock Synthesizer With 1.8V, 2.5V, and 3.3V LVCMOS Outputs datasheet (Rev. D) | PDF | HTML | 2025年 7月 23日 |
| Application note | Crystal or Crystal Oscillator Replacement with Silicon Devices | 2014年 6月 18日 | ||
| Application note | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 2012年 4月 23日 | ||
| User guide | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) | 2010年 11月 22日 | ||
| Application note | General I2C / EEPROM usage for the CDCE(L)9xx family | 2010年 1月 26日 | ||
| Application note | Troubleshooting I2C Bus Protocol | 2009年 10月 19日 | ||
| Application note | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 2009年 9月 23日 | ||
| Application note | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 2008年 3月 31日 |
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
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