DAC3482

現行

雙通道、16 位元、1.25-GSPS、1x-16x 內插數位轉類比轉換器 (DAC)

產品詳細資料

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
WQFN-MR (RKD) 88 81 mm² (9 mm × 9 mm) NFBGA (ZAY) 196 144 mm² (12 mm × 12 mm)
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

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設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TSW3085EVM — 寬頻發射訊號鏈評估板和參考設計

The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

使用指南: PDF
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開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式,v5.31

這款高速資料轉換器專業 GUI 是一款 PC(與 Windows® XP/7/10 相容)程式,旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡,為時域和頻域中的資料轉換器分析提供強大且快速的解決方案,並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容,可快速合成單音、多音和調變訊號。

使用者可以向 DATACONVERTERPRO-SW 提供自訂模式,以載入到 TI DAC。支援從 (...)

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開發模組 (EVM) 的 GUI

SLAC483 — DAC348x EVM Software GUI

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開發模組 (EVM) 的 GUI

SLAC507 — TSW308x EVM Software

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開發模組 (EVM) 的 GUI

SLLC420 — TSW3100EVM GUI v2.7

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模擬型號

DAC3482 IBIS Model (Rev. A)

SLAM073A.ZIP (33 KB) - IBIS 模型
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模擬型號

TINA-TI SPICE Models: Analog Interfacing Networks for DAC348x and Modulators

SLUC481.ZIP (198 KB) - TINA-TI Spice 模型
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參考設計

TIDA-00069 — 說明如何將 Altera FPGA 介接至高速 LVDS 介面數據轉換器的 FPGA 韌體範例

This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)

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參考設計

TIDA-00076 — 相鄰通道功率比 (ACPR) 和誤差向量幅度 (%EVM) 量測

此參考設計討論如何將 TSW3085EVM 搭配 TSW3100 模式產生器使用,以測試 LTE 基頻訊號的相鄰頻道功率比 (ACPR) 和誤差向量幅度 (EVM) 量測。使用 TSW3100 LTE GUI 將模式載入到 TSW3085EVM 中,該 EVM 由 DAC3482、TRF3705 和 LMK04806 組成。

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參考設計

TIDA-00077 — 適用於 DAC348x 和調變器的類比介面網路

此參考設計中的類比介面電路通常用於電流來源型數位轉類比轉換器 (DAC) 和正交調變器之間。雖然 DAC348x 可作為 TI 高速 DAC 範例,但只要稍加修改,電路仍可套用至其他電流來源轉換器。預設情況下,DAC348x 和 TRF3705 類比介面會安裝在 TSW308xEVM 上。DAC348x 與 TRF3705 皆採用相同的 DC 偏壓與 AC 擺幅規格,以提供無縫的介面。介紹其他電路拓撲,以考慮其他 DC 偏壓與 AC 擺幅規格。透過計算正確的 DC 偏壓和適當的 AC 擺幅,系統設計人員可以根據其應用需求套用這些電路,以實現最佳性能。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN-MR (RKD) 88 Ultra Librarian
NFBGA (ZAY) 196 Ultra Librarian

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