DAC38RF93
- 14-bit resolution
- Maximum DAC sample rate: 9 GSPS
- Key Specifications:
- RF full-scale output power at 2.1 GHz:
- DAC38RF80/90/84: 0 dBm
- DAC38RF83/93/85: 3 dBm (with 2:1 balun)
- Spectral performance(on-chip PLL, DIFF):
- fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
- WCDMA ACLR: 75 dBc
- WCDMA alt-ACLR: 77 dBc
- fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
- 20 MHz LTE ACLR: 63 dBc
- fDAC = 9 GSPS, fOUT = 1.8 GHz
- IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
- NSD = –157 dBc/Hz
- fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
- RF full-scale output power at 2.1 GHz:
- Dual-band digital up-converter per DAC
- 6, 8, 10, 12, 16, 18, 20 or 24x interpolation
- 4 Independent NCOs with 48-bit resolution
- JESD204B Interface, subclass 1
- Support for multichip synchronization
- Maximum lane rate: 12.5 Gbps
- Single-ended output with integrated balun (DAC38RF80/90/84) covering 700 MHz to 3800 MHz
- Internal PLL and VCO with bypass
- fC(VCO) = 5.9 or 8.9 GHz
- Power dissipation: 1.4 to 2.2 W/ch
- Power supplies: –1.8 V, 1 V, 1.8 V
- Package: 10 x 10 mm BGA, 0.8 mm pitch, 144-balls
The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.
The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL datasheet (Rev. D) | PDF | HTML | 2023年 12月 28日 |
Application note | Impact of Power-Supply Noise on Phase Noise Performance of RF DACs | 2018年 6月 13日 | ||
Application note | Eye Scan Testing with the DAC38RFxx | 2017年 8月 10日 | ||
Application note | Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information | 2017年 8月 2日 | ||
Application note | DAC38RF8x Test Modes | 2017年 7月 25日 | ||
Design guide | Efficient Power Supply Scheme for RF-Sampling DAC Reference Design | 2016年 8月 22日 |
設計與開發
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高速 DAC (>10 MSPS)
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支援產品和硬體
產品
高速 DAC (>10 MSPS)
發射器
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高速 ADC (≥10 MSPS)
超音波 AFE
射頻取樣收發器
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TIDA-01215 — 適用於最佳化射頻取樣 DAC 中的突波和相位雜訊的電源參考設計
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
FCCSP (AAV) | 144 | Ultra Librarian |
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