JFE2325
- Monolithic, matched, N-Channel JFETs
- Self-biased gates for high input impedance (>400GOhm)
- Low input capacitance: 0.85pF per JFET
- Low noise: ˗110dBV(A-wt.) with 5pF input capacitance
- Low VGS mismatch: 30mV (max)
- Low IDSS mismatch: 5% (max)
- High gate-to-drain breakdown voltage: 30V
- Extremely Small Package: 0.8mm × 1mm X2SON
The JFE2325 is a monolithic, matched-pair discrete JFET intended for use with very high-impedance sensors such as electret condenser microphones (ECMs). The device consists of two N-channel JFETs, laid out for excellent matching on a single die. The gate of each JFET is biased by an integrated diode which allows for direct coupling of a signal source to the gate without the need for a biasing resistor. The JFE2325 achieves much higher input impedance (>400GOhm) than possible if discrete resistors were used to bias the gate. Furthermore, the JFE2325 features an extremely low input capacitance of 0.85pF per JFET which maximizes signal levels from transducers with extremely low output capacitance.
Each JFET is capable of 0.7mS of transconductance when configured to run at the full drain current of 385µA. The JFETs can be used individually, or in parallel for higher transconductance and lower noise.
The JFE2325 can withstand a high gate-to-drain voltage of 30V. The temperature range is specified from –40°C to +125°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | JFE2325 Dual, Low-Power, N-Channel JFET for Electret Microphones datasheet (Rev. A) | PDF | HTML | 2026年 6月 18日 |
| EVM User's guide | JFE2325 Evaluation Module User's Guide | PDF | HTML | 2025年 12月 9日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
JFE2325EVM — JFE2325 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| X2SON (DTQ) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
- 晶圓廠位置
- 組裝地點